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REAP Code: 25
CAM:1025  RMCAAP:225   RMAT:278

VLSI Design using Verilog HDL Workshop on 11th September 2019

Date : 12 Aug 2020 | Category : Event

The Department of Electronics & Communication Engineering, RIET, Jaipur organized a webinar on “VLSI Design using Verilog HDL Workshop”, on 11th September 2019. The speaker of this event was Mr. P R Sivakumar – Founder & CEO, Maven Silicon who has 20+ years of experience in Semiconductor Industry. It was attended by all the faculty members and students of ECE, EE & EEE Departments.
During the session Mr. P R Sivakumar motivated and inspired the students towards the role and importance of VLSI design and application in Industry. He briefed about:
Overview of VLSI Design, Chips and SoCs , SoC Design, RTL Design using Verilog HDL, Data Types, Data type concepts, Verilog Operators , Concatenation and Conditional Operator precedence.